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Intel to Boost L2 Cache Capacity for Upcoming Arrow Lake CPUs

ahead of its expected launch. The latest bit of info states Intel is looking to beef up the amount of L2 cache for Arrow Lake's performance cores, or P-cores. It's a move that seems designed to blunt the impact of any V-Cache shenanigans AMD will deploy when the two enter the desktop CPU octagon once again in 2024.

The latest rumors come from a usually reliable source in China (via @9550pro), who has accurately predicted previous Intel hardware details months before their official unveiling. The user known as Golden Pig Upgrade is stating Intel plans to boost the amount of L2 cache in Arrow Lake's P-cores by 50%. The company will move from the 2MB per core on Raptor Lake to 3MB per core for its successor. This could give Arrow Lake a significant advantage over Alder and Raptor Lake in applications that depend on memory bandwidth. It also continues a trend that Intel has adopted, where it keeps adding more cache to each successive family of CPUs.

In comparison, when Intel launched Alder Lake in late 2021, it endowed those P-cores with just 1.25MB of L2 cache. That was beefed up for Raptor Lake, bumping it up to 2MB. By going to 3MB per core for Arrow Lake, Intel will crank things up to 24MB total for the 15900K or whatever it's called, assuming there will be eight P-cores still. It's unknown what Intel plans to do with the L3 layout for Arrow Lake, but Raptor Lake has 36MB of L3 total, spread out among its 12 clusters of P-and-E cores, so Arrow Lake could be similar, as noted by HotHardware.

Adding more L2 cache to Arrow Lake should improve performance by allowing some requests to fit into fast L2 memory instead of slower L3 or main system memory. There is still a lot we don't know about Arrow Lake's architecture, aside from that it will be based on the company's cutting-edge 20A process, which utilizes a tile-based design. When Arrow Lake debuts, it'll mark a new era for the company, as it will be its first disaggregated desktop CPU that uses gate-all-around (GAA) RibonFET transistors and backside power delivery. In other words, this is a whole different animal, and additional L2 cache is just one piece of a very complex puzzle.